The development of stacking technology for heterogeneous device integration has recently increased in importance.
Stacking of chips, in which two or more integrated circuits or ICs of different types are placed one on the top of the other in a same package, is an alternative to silicon integration and provides improvements at the system design level in terms of size, cost, speed, power consumption and ease of application for a wide variety of products.
In this field, the development of enhanced 3D interconnection systems is a process in order to enlarge the design space in new technologies implementation: having efficient and flexible vertical interconnection is often a requirement in order to be able to get new design guidelines about global nets optimization and chip partitioning. This is also a feature to be guaranteed in stacked devices in the scenario of the so-called Systems-on-Chip and Systems-in-Package.
In fact, stacking integrated circuits or silicon structures inside a same package and making them communicate may enhance the performance of a digital system comprising such structures as a whole, as described in the article to K. Banerjee et al.: “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration”, Proceedings of the IEEE, 89(5):602-633, May 2001, which is incorporated by reference.
Moreover, vertical data communication using AC wireless interconnect has been recently presented as a very promising stacking or 3D technology for high-bandwidth, high speed applications, as described in the article to Kanda K. et al. entitled “1.27 Gb/s/pin 3 mW/pin wireless superconnect wsc interface scheme”, ISSCC Dig. Tech. Papers, pp. 186-187, February 2003, which is incorporated by reference.
The known chip-to-chip vertical communication systems, as the ones described in the above referenced articles, are based on contactless 10 schemes exploiting capacitive coupling as an inter-chip channel. In particular, an upper metal layer of the technology process in which the system is manufactured is used to form a capacitive channel, as shown for instance in FIG. 1, a known type of chip-to-chip vertical communication system being globally indicated at 1 and hereinafter called briefly the system 1.
As shown in FIG. 1, the system 1 comprises a plurality of communication units 2, each comprising a transmitter 3 and a receiver 4.
In particular, the transmitter 3 resides on a first chip A and the receiver 4 resides on a second chip B, the first and second chips A and B being assembled in a stacked or 3D configuration, the first chip A being on the top of the second chip B and the transmitter 3 and the receiver 4 being positioned on respective facing surfaces of the chips A and B, more particularly chip A is face-down while chip B is face-up, with reference to an XYZ axis-system as shown in FIG. 1. The above configuration (transmitter 3-chip A; receiver 4-chip B) is considered only as an example, a reverse configuration (transmitter 3-chip B; receiver 4-chip A) being also possible, the same consideration applying.
The system 1 also comprises I/O interfaces 5 on both chips A and B.
Advantages of a 3D AC interconnection between chips, as the one illustrated in FIG. 1 are:                The interconnections are not based on DC contacts, and thus they are often highly reliable with respect to microbus or others DC connections;        there is often no need of using a protection circuit against electrostatic discharges (ESD);        the system 1 shows parasitic elements having reduced values; and        the system 1 has a great scalability.        
However, it may need an on-chip communication system should be also able to guarantee high performance, low power dissipation, reliability, and flexibility in data exchange for being useful in the majority of applications.
For complying with these requirements, major issues are about designing general purpose connections with good timing performances, and with low power consumption, comparable for instance with the ones related to on-chip global nets.
In this aim, an asynchronous capacitive interconnection system is more general with respect to a synchronous one, having:                a greater generality, since asynchronous signals and synchronous ones could be propagated with the same communication systems; and        a greater efficiency, since no dedicated clock tree is needed, avoiding the related power consumption and synchronization constraints.        
However, it should be reminded that a main issue about asynchronous capacitive interconnection systems remains, the minimization of power consumption.
Through capacitive elements such as the capacitive channel between transmitter 3 and receiver 4 in a system 1 like the one shown in FIG. 1, only AC signal components are transmitted. Thu, when a voltage transition occurs on an electrode of the transmitter 3, the voltage swing is propagated to an electrode of the receiver 4, with an attenuation that depends on the ratio between inter-electrode coupling and the input capacitive load related to the receiver 4. This behaviour of a capacitive transmission channel is shown for instance in FIG. 2 by means of a channel model, globally indicated by 6. In particular, the channel model 6 comprises a channel capacitor Ccc inserted between a first or transmitter node TX and a second or receiver node RX. Moreover, Ctx and Crx are the capacitive coupling to the voltage reference (here ground GND) of transmitter and receiver nodes. Due to this attenuation, the design of the receiver circuit is important. For example, if the attenuation is significant the receiver may require a high-gain, and this may require spending a lot of power consumption for biasing the circuit. On the other hand, the reduction of power consumption for asynchronous communication circuits usually implies a worst-case sensitivity and thus a large area for the electrodes.
Many architectures have been proposed for implementing an interconnection system and/or a receiver circuit thereof.
Such known architectures are described, for instance, in the article to R. Drost et al. entitled: “Proximity Communication”, CICC2003, to S. Mick et al. entitled: “4 Gbps High-Density AC Coupled Interconnection”, CICC2002 and in the article to Luo et al. entitled: “3 Gbps AC-Coupled Chip-to-Chip Communication Using a Low-Swing Pulse Receiver”, ISSCC2005, which are incorporated by reference.
Other interconnection systems are described in the U.S. Pat. Nos. 6,600,325 and 5,629,838, which are incorporated by reference.
These known solutions may have a power-consumption vs. electrode-area trade-off in the design of the receiver element.